Wus Bets on VeCS for High-Layer-Count HDI PCBs

NextGin Technology’s VeCS vertical conductive structure has moved into commercial use at PCB fabricator Wus, nearly a decade after inventor Joan Tourné first secured the IP. The process targets high-density interconnects for complex, high-layer-count HDI PCBs and large backplane-type boards. With semiconductor and advanced packaging demand rising, VeCS is being re-examined as a viable HDI fabrication option for OEMs.

VeCS replaces conventional plated through-holes or microvias with a vertical slot or trench structure, enabling higher interconnection density in thick, high-layer-count PCBs. Developed by NextGin Technology and now deployed in Wus factories, the method is designed for backplane and server-class boards where routing density, signal integrity, and thermal management are critical. Unlike stacked microvias, VeCS can span multiple layers without sequential lamination steps, reducing drill count, improving yield, and lowering cost for large-format boards used in networking, telecom, and data center equipment. For HDI PCB buyers, VeCS offers a middle path between standard PTH and expensive any-layer microvia construction, especially for boards above 20 layers where aspect ratio limits make traditional drilling impractical. Wus has integrated VeCS into its high-volume fabrication lines, signaling that the technology has cleared reliability and manufacturability hurdles.

Renewed interest in VeCS aligns with tightening design rules for AI servers, 5G infrastructure, and high-performance computing. High-layer-count PCBs often struggle with plated through-hole aspect ratio limits, and advanced HDI alternatives like any-layer microvias add significant cost and yield risk. VeCS provides vertical conductive structures that support dense routing in thick boards without the full expense of sequential lamination. For OEMs and EMS providers sourcing backplane and high-layer-count boards, VeCS represents a process option to track alongside mSAP, substrate-like PCBs, and glass core technologies. As chip scaling slows, advanced packaging and PCB-level interconnect density are becoming the new battleground, and vertical interconnect innovations like VeCS could help bridge the gap between conventional PCB fabrication and IC substrate demands. The re-examination by I-Connect007 this month reflects growing industry attention on alternative HDI methods that can scale for complex, high-reliability applications.

For PCB buyers evaluating HDI any-layer or high-layer-count programs, the VeCS deployment at Wus signals that vertical interconnect innovations are entering volume production. LT CIRCUIT tracks these process shifts closely, offering HDI, multilayer, and substrate-like PCB capabilities that align with the industry’s move toward denser, higher-reliability interconnect structures for advanced electronics and semiconductor packaging.